GMT Technology Primer
GMT's relative timing technology provides impressive competitive advantage to our customers in the semiconductor industry. The advantages of GMT's technology come primarily in the following metrics: • power • area • performance • power supply and EMI noise • system integration • PVT robustness.
Robust and energy efficient muti-frequency designs are achieved using our relative timing technology. Relative timing provides three primary advantages to the way that traditional designs are created today. First, relative timing formally proves correctness of all timing conditions in your designs. Thus timing closure is simplified and you know circuit timing will be correct. Second, it directly supports all circuit and system level timing methodologies. It is equally compatible with traditional clocked, dynamic logic, and unclocked asynchronous circuit designs and system architectures. Thus it provides a unifying formalism that bridges clocked flows and more aggressive dynamic and asynchronous logics. Third, relative timing is completely compatible with traditional design flows used by the industry today. Therefore one can employ Verilog for the HDL, timing and power driven synthesis and place & routing, and timing verification as is done in traditional ASIC flows to create clocked, dynamic, and asynchronous circuits and systems that operate at various disparate frequencies.
The judicious or aggressive use of timing methods and frequencies in a design is enabled with relative timing due to its unifying timing formalism and compatibility with the traditional CAD flows. The method is so robust that one may even include sections of asynchronous logic into predominantly clocked design if this creates substantial design advantages. Energy and design efficiencies are generally derived from three primary benerits this technology enables. First, communication can be performed by formal handshake protocols, which results in fine grain clock gating not possible with traditional clocked designs. Second, most designs today operate most efficiently at multiple frequency domains, enabling better performance, power and noise optimization points in the local and system level designs. This advantage is coupled with an improved ease of system level integration. Third, design blocks can be made "dark" or "reactive" in such a way that reduces power yet does not compromise performance.
Rock Solid, Robust Technology
A completely new approach to robust low power and high performance can be achived through relative timed design.
Timing is the key difference between traditional clocked and relative timed design. Relative timed ICs will often contain various frequencies as each block is optimized for power, area, and performance both locally and in the system as a whole. Some design modules may even operate on a time scale that is continuous, rather than the traditional discrete time domains. Such an approach is extremely challenging to design and validate without GMT technology. Relative timing allows the essential timing relationships between modules and fixed frequencies to be explicitly and cleanly represented throughout the design flow using commercial EDA for design and signoff.
Robust multi-frequency design is made possible through GMT's relative timing technology. The foundations of relative timing lie in formal methods. Therefore all timing requirements of a circuit are formally proven sufficient and complete for any circuit to work correctly. This methodology provides three outstanding advantages:
- Because it is based on formal methods, all necessary timing conditions for performance and correctness will be specified and formally verified for every design.
- Because it is general, the model works for all circuit design methodologies, including clocked, asynchronous bundled data, as well as delay insensitive approaches such as dual-rail and null convention logic, as well as dynamic logic blocks.
- Since this timing model applies equally to single as well as multi-frequency design, this theory produces complete compatibility with traditional clocked design and tool flows. Thus multi-frequency designs can be synthesized, optimized, tested, and validated with as many different frequencies as needed to create efficient low power circuits.
Relative Timed Design is NOT the same as Clocked Design
A good single frequency clocked system architecture has many similarities as well as differences with an analogous optimized for power, performance, and area using relative timing. In general, one can start with single frequency clocked RTL specified in Verilog and transform this design into a multi-frequency design that has improved power and performance. A number of architectural changes will occur in this process to derive advantages. This may include creating regions of the design that operate at the best local frequency for power and performance, adding fine grain clock gating and power gating. The frequency targets for each region is specified independently. Often adding a handshake protocal for transfers between clock domains simplifies the system integration and produces more robust circuits. The choice of protocols is dependent on the properties of the specific design or module, and may be enhanced with GMT specific IP blocks. The data path of the design largely remains identical to that of the original single frequency design. This enables, for example, the same test strategy to be employed in the multi-frequency design as in the original single frequency clocked design.
GMT provides optimized IP blocks for integrating different frequency domains. This IP is supported by all traditional cell libraries and passes through the same design flow that our customer's currently employ. Additional relative timing constraints will be added to the flows at various stages of the design to ensure that interfaces between frequency domains are correctly optimized and validated.
GMT provides implementation services to help translate your single frequency clocked IP into low power designs, giving you a significant competitive advantage over your competitors.