The ecosystem of digital circuit design has seen tremendous growth in areas of tools, process technologies, verification, validation and languages, but very little growth in the style of digital design. Even today, designers are bound to a narrow view of digital design that involves clocked finite state machine styles that were established in the 1970s. GMT’s Relative Timing technology is a proven and mature methodology that enables designers to use innovative design styles not possible with the traditional approach. This often results in circuits that are smaller, faster and lower power.
Relative Timing Technology Overview
The Basics of Relative Timing
Correct functional operation of every digital circuit is a result of two things: logic and timing. Relative Timing (RT) creates a design methodology that opens up both the logic and timing of a circuit to innovation.
In its simplest form, RT orders events within a circuit to guarantee functional correctness. For instance, consider Fig. A that represents a race between two paths. The first path (shown in orange) goes through block A from the point-of-divergence (POD) to the point-of-convergence (POC) through path POC0. The second path (shown in green) goes through block B from the POD to the POC through POC1. For this circuit to function correctly, the signal through block A, arriving at POC0, needs to arrive before the signal through block B, arriving at POC1.
RT formally represents, enforces, and maintains the required ordering of events to guarantee functional correctness of the implemented logic. The formal representation of the event ordering requirement in Fig. A – called a RT constraint – can be seen in equation 1:
POD → POC0 + margin ≺ POC1 (1)
This RT constraint requires the maximum delay of the path to POC0 to be less than the minimum delay of the path to POC1 with some measure of margin. Similarly, the RT constraint for the circuit in Fig. B comprising of two register stages can be seen in equation 2:
clki → FF1/data + setup ≺ FF1/clki+1 (2)
This is a representation of a regular clock system, where the data being registered at FF0 following clki needs to arrive at FF1 before the next clock, clki+1. The clki, FF1/data and FF1/clki+1 are analogous to the POD, POC0 and POC1 of equation 1. Further, the margin mentioned in equation 1 translates to the needed setup time for FF1 in Fig. B.
Applying Relative Timing to a traditional counter circuit
An example of a simple counter circuit illustrates how Relative Timing can be leveraged to create circuits with reduced power and area. Fig. C shows the implementation of a counter using a traditional clocked flow. This is a simple register bank that is driven by combinational logic that carries out the incrementation function. Fig. D shows the implementation of a counter that is implemented using RT: a cascade counter.
The critical paths in Fig. C and Fig. D are highlighted in orange (these would be the FF0 register bank in Fig. B). Traditional clocked timing validation flows will not validate the design implemented in Fig. D because timing paths are cut between the clock and Q ports of the flip-flops. Relative timing allows the timing path in Fig. D to be evaluated as it cascades through the flip-flops.
An RT constraint that propagates the registers is used to create a timing requirement that can then be implemented in conjunction with the timing requirements of the environment that surrounds the counter, even if the environment is a traditionally clocked finite state machine. The RT cascade counter provides up to an 80% reduction in active power and 50% reduction in area, depending on the available margin in the delay path.
Using RT to gain advantages implementing different design styles
Relative Timing enables designers to use innovative design styles in ways that weren’t previously considered due to the nature of clocked design. Designers can now be flexible and leverage the entire spectrum of design styles – from clocked to handshake designs – based on the requirements and possibilities for optimization.
An example of a simple decimator circuit that changes frequency domains illustrates how a designer can optimize a design by using a different design style with RT. Fig. E shows the implementation of a decimator using a traditional clocked flow. In this particular case, this clocked decimator circuit can be implemented as a handshake-based RT design, as shown in Fig. F. The handshake-based RT approach produces a design that is smaller, lower latency, and lower power than the clocked design.
The handshake-based RT design uses request and acknowledge signals to move data. The left-request (lr) and left-acknowledge (la) are used to handshake with the upstream data stage. The right-request (rr) and right-acknowledge (ra) are used to handshake with the downstream data stage.
Relative Timing is universal in nature. This allows RT to take advantage of any kind of design style, and to take the “best of all worlds” in terms of design optimizations and styles.
Relative Timing Validation Flow connect to traditional CAD flows
The functional correctness of a circuit built with RT is proven through formal models. Since circuit timing is formally proven, RT can guarantee that the circuit will not fail due to timing. This is done in a design by integrating the RT Formal Verification tool flow with existing CAD tools flows as shown in Fig. G.
Relative Timing Formal Verification tools take a functional specification, a design, and user-defined RT constraints (in Fig. G, the same constraint used in Fig. B) as inputs and generate any additional constraints needed to ensure that the design conforms to the functional specification. Traditional EDA tools are then utilized to implement the design along with the RT constraints through various implementation stages such as synthesis and physical placement, while using static timing analysis tools to verify the implementation of the constraints and optimize the performance of the circuit.
Relative Timing provides competitive advantages to digital circuits
Companies that take full advantage of GMT’s Relative Timing technology reap the benefits of competitive advantages in the digital circuit domain. The following table highlights a few SoC subsystems that have achieved significant power, performance, area, and latency benefits through an RT implementation vs. a more traditional approach:
Using Relative Timing today
Today, companies can access the benefits of Relative Timing through GMT design services and turnkey solutions. GMT has implemented and fabricated multiple RT designs for customers in process nodes ranging from 180nm down to 12nm, with a 5nm design currently under implementation.
GMT’s roadmap includes making available its in-house CAD tools to enable hard IP, soft IP, and ultimately do-it-yourself solutions for customers seeking to adopt Relative Timing for their digital design.
Contact GMT today to start your Relative Timing implementation to outpace the competition.