The employee may work on all aspects of relative timed circuit technology. This includes work ranging from the specification and development of small templates that can be integrated into the design flow, as well as the development of low power systems. Skill in all levels of circuit design are required, including flow tables, boolean logic, understanding of the properties of deep submicron design, process variation, circuit timing and sizing, the effects of voltage scaling, etc. The ability to transform and optimize designs to meet user specified criteria through architectural concurrency changes and circuit level modifications is essential. Primary design criteria the designer must optimize include power/energy, performance, area, test coverage, noise, timing margins, and other targets. Skill using ASIC CAD tools including the Synopsys, Cadence, and Mentor Graphics flows is required. The user should be familiar with scripting using perl and tcl. Experience with programming C++ is a plus. Experience with relative timing or asynchronous design is helpful. Experience: Preferred M.S. or greater with 4-5 years of industry experience.