Hardware design is ripe for innovation

As artificial intelligence, edge computing, and other high-performance, low-power applications become increasingly common market solutions across nearly all industry verticals, the importance of the hardware on which these applications are built is increasing. The demands on hardware to satisfy software requirements have never been greater.

For decades, the industry’s solution to lower power, better performance, and smaller area has been technology scaling. The principle of technology scaling and Moore’s Law is that the speed and capability of integrated circuits doubles roughly every two years as more and more transistors are squeezed into a smaller area on the wafer.

For many decades, Moore’s Law has played out as predicted, and has provided the much-needed advances in hardware to satisfy the demands from applications and software. However, after decades of unparalleled power-performance-area (PPA) advances, we are reaching the tipping point of Moore’s Law. Many industry leaders in the largest technology companies around the world are now predicting the slowing of the benefits of technology scaling, with some predicting the death of technology scaling as we know it today.

Relative Timing is the innovation hardware needs

With the slowing of Moore’s Law, companies are looking to other methods for gains that were once guaranteed through scaling. GMT has developed a novel, patented technology called Relative Timing (RT) that enables hardware designers to reap untapped design benefits, and provides competitive advantages in the following metrics:

• • Power
  • Performance
  • Area
  • Power supply & EMI noise
  • PVT robustness
  • System integration
  • Time-to-market

Relative Timing is event ordering

Timing is the key difference between a more traditional design style commonly used today and a Relative Timing design style and approach.

In its simplest form, Relative Timing provides event ordering for data moving through the many paths of a circuit. Through generating a special form of constraints called RT constraints, an RT methodology ensures that data through a circuit will arrive at its destination(s) in the correct order to ensure correct timing for circuit functionality.

Relative Timing is based in formal proofs

The foundations of RT lie in formal methods. A formal method is a system design technique that uses mathematical models to prove the necessary timing conditions in a system are formally verified to be correct.

GMT’s RT methodology uses mathematical models to formally prove the correctness of all timing conditions in a circuit. Thus, all timing requirements of a circuit built with RT are formally proven and guaranteed to be correct.

Relative Timing formal methods are general and can be applied to any design or design style.

Relative Timing enables innovative design

GMT’s innovative approach to addressing the timing of a circuit enables hardware designers to experiment with design in ways that traditional designers can’t. Traditional clocked design methodologies employ a much more rigid view of timing. This view – while helpful and even needed to usher in the incredible growth of hardware design over the past few decades – limits a designer’s ability to leverage timing as a design asset for greater optimizations.

Relative Timing can be used with any design style

Relative Timing can be applied to traditional clocked design methodologies to extract competitive advantages. Unlike most designers, however, those using a Relative Timing methodology aren’t limited to clocked design styles; benefits can be realized through expanding the universe of what styles can be employed to extract even greater competitive advantages.

Circuits can be designed with RT using the following methodologies: traditional clocked, dynamic logic, asynchronous bundled data, delay insensitive approaches such as dual-rail and null convention logic, and handshake-based protocols.

RT is so robust, that SoCs can be built with a more piece-meal approach, with various design styles employed in a single design. For example, a predominantly clocked design could include sections of asynchronous logic if this created a more efficient design.

ICs designed with RT can be designed at a single frequency, but will more often contain various frequencies as each block is optimized for power, performance, and area both locally and in the system as a whole. Some design modules may even operate on a time scale that is continuous, rather than traditional discrete time domains. Such an approach is extremely challenging to design and validate without RT.

Relative Timing integrates into traditional CAD tool flows

Relative Timing allows the essential timing relationships between modules and fixed frequencies to be explicitly and cleanly represented through the design flow using commercial EDA for design and signoff.

To use RT for design, RT constraints are created. Timing constraints, functional specifications and the IC design are fed into RT formal verification tools. The output of these tools are special timing constraints called RT constraints that can be fed directly into the traditional CAD flow.

Therefore, a designer can employ Verilog for HDL, timing and power-driven synthesis and place & routing, and timing verification as is done in traditional ASIC flows. The flow needed to create RT-based circuits is effectively the same; a few steps are inserted at key points to ensure that the RT constraints are seamlessly integrated into the design flow.

Transforming design with Relative Timing

Using Relative Timing, designs can be enhanced and optimized. An engineer could start with a single frequency clocked RTL specified in Verilog and transform it into a multi-frequency design that has improved power and performance.

A number of architectural changes could occur in this process to derive advantages. Designers could create regions of the design that operate at the best local frequency for power and performance, adding fine grain clock gating and power gating. They could include frequency targets specified independently for different circuit regions. They could include adding a handshake protocol for transfers between clock domains to simplify system integration.

In most cases, even with these types of architectural changes, the data path of the design would remain largely identical to that of the original single frequency design. This would enable, for example, the same test strategy to be employed in the multi-frequency design as in the original single frequency clocked design.

Using Relative Timing today

Today, companies can access the benefits of Relative Timing through GMT design services and turnkey solutions. GMT has implemented and fabricated multiple RT designs for customers in process nodes ranging from 180nm down to 12nm, with a 5nm design currently under implementation.

GMT’s roadmap includes making available its in-house CAD tools to enable hard IP, soft IP, and ultimately do-it-yourself solutions for customers seeking to adopt Relative Timing for their digital design.

Contact GMT today to start your Relative Timing implementation to outpace the competition.